1. Technical Field
Exemplary embodiments disclosed herein relate to phase change memory devices, and more particularly, to a phase change memory (PRAM) device having a bit-line discharge block.
2. Related Art
Semiconductor memory devices are generally classified into volatile and nonvolatile types. Typically volatile memory devices are random access memories (RAMs) that lose their data when power is interrupted. Typically nonvolatile memory devices are read-only memories (ROMs) that are capable of retaining their data even when power is interrupted. Some typical RAMs include dynamic and static RAMs, while some typical ROMs include flash memories.
The dynamic RAM (DRAM) devices typically enjoy low power consumption and random access advantages, but suffer by being volatile as well as suffer by having relatively large increases in the volume of cell capacitors due to the demands for larger data capacities. The static RAM (SRAM) devices usually employed as caches in systems can realize the advantages of speed as well as convenience due to random access. However SRAM devices also suffer by being volatile and suffer by being relatively more expensive per bit due to their relatively large cell sizes. In contrast flash memories are nonvolatile but they suffer from requiring operation voltages higher than power source voltages because two gates (e.g., control and floating gates) are stacked in each cell structure. As a result flash memories additionally require voltage boosting circuits for supplying high voltages to memory cells in the writing and erasing modes. For these and other reasons flash memories are not easy modify in order to improve higher integration densities and to enhance their relatively slower operation rates.
In consideration of the above structural and functional limitations of the semiconductor memories, there have been a number of different proposed alternate memory configurations that include ferroelectric RAMs (FRAMs), magnetic RAMs (MRAMs) and phase change RAMs (i.e., PRAMs).
The PRAM devices typically include a phase change transition material that exhibits a relatively high resistance when in a disordered amorphous state and exhibits a relatively low resistance when in a more ordered crystalline state. Information can be stored in PRAMs by writing and reading the corresponding resistance across the phase change material. The PRAM is regarded as more advantageous than the flash memory in promising to realize higher operation rates and higher integration densities.
A PRAM memory cell may be formed of a switching element coupled to a word line, a page changeable material heating up/down by an on/off condition of the switching element, and a bit line transferring data into/from the phase change material.
A writing operation of the PRAM is accomplished by applying a current to the phase change material of a selected memory cell through a corresponding bit line that reversibly drives the phase change material into either the amorphous or crystalline solid states. A writing data of “0” (set) or “1” (reset) can be arbitrarily assigned to anyone of the particular solid states of the phase change material.
Data from the PRAM can be read by correlating the resistivity across of the particular solid state phase of the phase change material. When only two major solid state phases occur between each other in a given phase change material, then logical values of data can be arbitrarily assigned as either “0” or “1” depending upon the measured resistance subsequent to a writing operation.
The PRAM devices usually employ a bit-line discharge switch at an end of each bit line for correctly reading and writing data. The bit-line discharge circuit generally includes a MOS transistor that functions to preliminarily exhaust charges out of the bit line.
To increase of integration density on the PRAM in recent years, a vertical PN diode has been used to replace the MOS transistor of a cell switching element to realize a smaller occupation area of each PRAM cell. Thus, owing to a burden of building a MOS transistor region in a cell array field for the conventional bit-line discharge switch formed of the MOS transistor, there is a problem of enlarging a layout size on the PRAM.
Considering the area burden relevant to the structure of bit-line discharge switch, Korean Patent No. 0887069 discloses that the bit-line discharge switch is formed of a dummy cell in the same pattern with a PRAM cell.
As illustrated in FIG. 1, dummy cells 20 are each coupled to ends of bit lines BL1˜BL4. Each dummy cell is composed of a switching diode D and a variable resistor Rv made of a phase change maternal, as like the structure of PRAM cells 10 arranged at intersections of word lines WL1˜WL4 and the bit lines BL1˜BL4.
With the dummy cells 20, when a bit-line discharge signal BLDIS is activated in a low level, a ground voltage is transferred to the bit lines BL1˜BL4 by way of the switching diode D and the variable resistor Rv. Then, the bit lines BL1˜BL4 are discharged to the ground voltage.
This structure as shown in FIG. 1 may be regarded as helpful in reducing a size of the PRAM layout by building the bit-line discharge switch in the same structure with the PRAM cell 10 because there is no need to prepare a MOS transistor region in a cell array field as well as no need to prepare an additional circuit for extending discharge paths of the bit lines.
However, in the discharge switch of the dummy cell 20 much like in the PRAM cell 10, the variable resistor Rv of the dummy cell 20 is composed of a phase change material. As a result the variable resistor can inadvertently change phases be changed in response to a pulse of the bit-line discharge signal BLDIS even at low heat conditions.
Such an inadvertent phase change of the variable resistor Rv of the dummy cell 20 would cause an unwanted discharge failure to a corresponding bit line and further incur an error of reset data from the PRAM cells 10 coupled to the corresponding bit line, resulting in a column fail.